This role at Apple involves contributing to all phases of physical design for high-performance PHY design, from RTL to GDSII delivery. The position is based in Waltham, Massachusetts, and focuses on developing and validating low power clock network guidelines while ensuring design meets timing, area, and power constraints. The team emphasizes innovation and collaboration, leveraging diverse ideas to create groundbreaking products. Candidates will engage in physical design verification and assist in establishing methodologies for correct-by-construction designs.

• Master's degree or foreign equivalent in Electrical Engineering or a related field.
• Experience in modeling and characterizing digital CMOS devices.
• Knowledge of logic gates, latches, PLA, ROM, and RAMs.
• Experience in design, layout, and fabrication of CMOS mixed signal integrated circuits.
• Proficiency in performing static timing analysis and timing validation.
• Ability to analyze interconnect and parasitic elements.
• Experience using System Verilog for hardware verification.
• Skills in designing and analyzing high-speed logic and memory.

• Contribute to all phases of physical design from RTL to GDSII delivery.
• Generate block and chip level static timing constraints.
• Build full chip floorplan including pin placement, partitions, and power grid.
• Develop and validate high performance low power clock network guidelines.
• Perform block level place and route to meet timing, area, and power constraints.
• Generate and implement ECOs to fix timing, noise, and EM IR violations.
• Run physical design verification flow at chip/block level.
• Provide guidelines to fix LVS/DRC violations to other designers.
• Participate in establishing CAD and physical design methodologies.
• Assist in flow development for chip integration.
• Perform PnR using Cadence Innovus and Prime Time tools.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.