As an ASIC STA Engineer at Apple, you will be part of a dynamic team focused on leading edge IP development and SOC design. Your role will involve collaborating with multiple SOC teams to ensure high quality IP deliverables. You will take ownership of full chip and block level timing closure throughout the project lifecycle. This position offers the opportunity to work on advanced Apple SoC chips targeted for high-end mobile applications.

• Bachelor's Degree in a relevant field.
• 3 years of experience in digital design.
• Strong fundamentals in digital design concepts.
• Proficiency in scripting languages such as TCL and Perl.
• Familiarity with ASIC design timing concepts.

• Lead timing closure ownership for full chip and block level designs.
• Develop and maintain methodologies and flows for timing verification.
• Generate block and full chip timing constraints.
• Collaborate with multi-functional teams to resolve complex timing issues.
• Work on Apple SoC chips in deep sub-micron technologies.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.