As an ASIC STA Engineer at Apple, you will be part of a dynamic team focused on leading edge IP development and SOC design. Your role will involve collaborating with multiple SOC teams to ensure high quality IP deliverables. You will take ownership of full chip and block level timing closure throughout projects, while also developing methodologies related to timing verification. This position offers the opportunity to work on advanced Apple SoC chips aimed at high-end mobile applications.

• Bachelor's degree in a relevant field and at least 3 years of experience.
• Strong fundamentals in digital design.
• Proficiency in scripting languages such as TCL and Perl.
• Familiarity with ASIC design timing concepts.
• Exposure to STA tools like Primetime is a plus.
• Knowledge of timing corners, process variations, and signal integrity issues is advantageous.

• Lead the design and integration tasks for high quality IP deliverables.
• Own full chip and block level timing closure throughout the project.
• Develop and maintain methodologies and flows related to timing verification and closure.
• Generate block and full chip timing constraints.
• Collaborate with multi-functional teams to resolve complex timing issues.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.