The CPU Microarchitect/RTL Engineer role at Apple involves driving the architecture and RTL development of multi-level cache subsystems for multi-processor systems. This position is part of Apple's Silicon Engineering Group, which focuses on designing high-performance, low-power microprocessors for innovative products. The engineer will engage in micro-architecture development, RTL ownership, and performance exploration. A strong emphasis is placed on collaboration with multi-functional engineering teams to ensure design delivery meets various performance and power goals.

• Minimum BS degree in a relevant field
• Experience with Verilog or VHDL programming languages
• Expertise in instruction fetch and decode, branch prediction, or cache and memory subsystems
• Understanding of low power microarchitecture techniques
• Experience in C or C++ programming
• Familiarity with interpretive languages such as Perl or Python

• Develop and specify micro-architecture from high-level exploration to detailed specifications
• Own the development and refinement of RTL design to meet power, performance, area, and timing goals
• Support the verification team in developing test benches and formal verification methods
• Explore high-performance strategies and verify RTL design performance with the verification team
• Collaborate with engineering teams to implement and verify physical design aspects

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.