As an SOC/ASIC Integration & Synthesis Engineer at Apple, you will be part of a dynamic team focused on defining methodologies and flows for complex chip implementations. Your role will involve driving front-end integration activities and improving synthesis quality of results. You will collaborate closely with various engineering teams to ensure low power design and effective timing analysis. This position requires a passion for problem-solving and a commitment to delivering innovative solutions.

• BS degree in a relevant field plus 10 years of industry experience is required.
• Expertise in digital design integration, synthesis, UPF, timing analysis, and closure.
• Experience with scripting languages like Perl, Tcl, or Python.
• Familiarity with modern AI tools and platforms.

• Drive all front-end integration activities including Integration, Synthesis, UPF, Logical Equivalence, and ECO.
• Work closely on methodology improvements to enhance synthesis quality of results.
• Engage in low power design, writing UPFs, and verifying power intent at the chip level.
• Conduct RTL integration, timing constraints, and synthesis of designs.
• Collaborate with SOC Design, SOC Design Verification, Emulation, STA, Power, and Physical Design teams.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.