The Senior Physical Design Flow and Methodology Engineer at Google will focus on shaping the future of AI/ML hardware acceleration by driving cutting-edge TPU technology. This role involves developing flows, methodologies, and data management systems for physical design EDA tools within the Google Compute Engine environment. The engineer will collaborate with chip design teams to implement tools and methodologies for physical design in leading-edge process nodes. This position is part of a team that empowers Google customers with breakthrough capabilities and insights through innovative AI and infrastructure solutions.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with physical design flow and methodologies.
• Experience with EDA tools for physical design such as Cadence, Synopsys, or Siemens.
• Experience in full-chip or block-level physical design.
• Experience with scripting in Python, Tcl, or Perl.

• Architect and implement next generation physical design EDA and CAD tool workflows for ASIC development.
• Collaborate with chip design teams to implement tools and methodologies for physical design in leading edge process nodes.
• Develop auditing tools, checkers, and metric dashboards based on APIs from third-party EDA tools.
• Own the physical design of blocks and subsystems end-to-end.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.