Apple's Silicon Engineering Group is seeking a dedicated CPU Gate Level Synthesis Engineer to join their industry-leading CPU design team. This role focuses on assessing and optimizing design quality for high-performance, low-power digital designs. The engineer will work in a multi-functional capacity to ensure CPUs meet high standards for performance, power, and area. Collaboration with various teams is essential to implement methodologies and optimize designs.

• Minimum BS degree and 3+ years of relevant industry experience
• Experience in digital logic design, RTL synthesis, and physical design
• CPU implementation experience is preferred
• Proficiency in scripting languages such as TCL, Perl, and Python
• Strong problem-solving, debugging, and collaboration skills

• Conduct early RTL health assessments to identify potential timing and gate-depth issues
• Perform early stage power estimation and validation for new micro-architectural features
• Enhance synthesis flows to ensure high fidelity of synthesis-based feedback
• Collaborate with DFT teams for seamless integration of scan chain, ATPG, and MBIST
• Partner with the timing team to enable constraints generation at top levels
• Debug and resolve timing, power, and area issues to ensure efficient designs
• Track and analyze PPA trends throughout the project cycle

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.