Apple's Silicon Engineering Group is seeking a dedicated CPU Gate Level Synthesis Engineer to enhance design quality for high-performance CPUs. The role involves optimizing digital designs for performance, power, and area while collaborating with cross-functional teams. The engineer will be responsible for early-stage development and validation of micro-architectural features. This position requires a strong background in digital logic design and synthesis methodologies.

• Minimum BS degree and 10+ years of relevant industry experience
• Experience in digital logic design, RTL synthesis, and physical design
• CPU implementation experience is preferred
• Proficiency in scripting languages such as Tcl, Perl, and Python for automation
• Strong problem-solving and debugging skills

• Conduct early RTL health assessments to identify timing and gate-depth issues
• Perform early stage power estimation and validation for new micro-architectural features
• Enhance synthesis flows to ensure high fidelity of synthesis-based feedback
• Collaborate with DFT teams for seamless integration of scan chain, ATPG, and MBIST
• Partner with the timing team to enable constraints generation at top levels
• Debug and resolve timing, power, and area issues for efficient designs
• Track and analyze PPA trends throughout the project cycle

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.