The Design Verification Engineer role at Apple focuses on verifying the functionality and performance of Apple's premier SOCs. This position is critical within Apple's Hardware Technology team, where collaboration with design and micro-architecture teams is essential. The engineer will ensure the quality of SOCs and subsystems by developing test plans and methodologies. This role requires strong communication skills and the ability to work independently to achieve project goals.

• Minimum of a BS degree and 3 years of relevant industry experience.
• Skilled in digital verification processes including constrained random verification, functional coverage, and code coverage.
• Knowledge of Verilog/SystemVerilog, digital simulation, and debugging.
• Understanding of computer architecture and digital design fundamentals.
• Exposure to UVM is desired.
• Experience with C/C++ and assembly is a plus.
• Familiarity with Perl, Python, or similar scripting languages.

• Review design and architecture specifications to ensure quality.
• Develop test plans, tests, and coverage plans for SOCs.
• Collaborate with design, architecture, and software teams to understand use cases and corner conditions.
• Run and triage regressions, track bugs, and analyze coverage.
• Drive the creation of test cases based on functional and performance goals.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.