As a Design Verification Engineer at Apple, you will be integral to the chip design process, ensuring the functionality and performance of Apple's premier SOCs. You will collaborate with various teams to review design specifications and develop comprehensive test plans. This role requires a deep understanding of functional and performance goals to effectively drive testing efforts. Your contributions will help shape the next generation of verification methodologies and testbenches.

• Minimum of a BS degree with 0 years of relevant industry experience.
• Knowledge of computer architecture and digital design fundamentals.
• Familiarity with Verilog or SystemVerilog, digital simulation, and debugging.
• Experience with Python, Perl, or similar scripting languages.
• Ability to work independently to achieve project goals.
• Experience with C/C++ and assembly is a plus.
• Excellent interpersonal skills and a willingness to tackle diverse challenges.

• Verify the functionality and performance of SOCs and subsystems.
• Review design and architecture specifications.
• Develop test plans, tests, and coverage plans.
• Define next generation verification methodology and testbenches.
• Communicate and collaborate with design, architecture, and software teams.
• Run and triage regressions, track bugs, and analyze coverage.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.