The Design Verification Engineer role at Apple focuses on verifying the functionality and performance of Apple's premier SOCs. You will be part of a dedicated team at the heart of the chip design effort, collaborating with various teams to ensure quality. This position requires a strong understanding of design specifications and performance goals to develop effective test plans. You will also engage in communication with design, architecture, and software teams to drive test cases and achieve top results.

• Minimum of a BS degree with 0 years of relevant industry experience.
• Knowledge of computer architecture and digital design fundamentals.
• Knowledge of Verilog or SystemVerilog, digital simulation, and debug.
• Experience with Python, Perl, or a similar scripting language.
• Experience with C/C++ and assembly is a plus.
• Excellent interpersonal skills and a desire to take on diverse challenges.

• Review design and architecture specifications to ensure quality.
• Develop test plans, tests, and coverage plans.
• Define next generation verification methodology and testbenches.
• Run and triage regressions, track bugs, and analyze coverage.
• Collaborate with design, architecture, and software teams to understand use cases and corner conditions.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.