In this highly visible role at Apple, you will be responsible for implementing complete chip design from netlist to tapeout. You will work closely with the front-end team to understand chip architecture and drive physical aspects early in the design cycle. The position requires collaboration with the physical design team to streamline methodologies and track progress. Your expertise will be crucial in resolving design and flow issues related to physical design.

• Minimum BS degree with 10+ years of experience.
• Familiarity with ASIC integration aspects including floorplanning, clock and power distribution, and I/O planning.
• Experience with SoC issues such as multiple voltage and clock domains and mixed signal block integration.
• Understanding of hierarchical design approaches and physical convergence.
• Experience integrating IP from both internal and external vendors.

• Implement complete chip design from netlist to tapeout.
• Work with the FE team to understand chip architecture and drive physical aspects early in the design cycle.
• Collaborate with the physical design team to drive methodologies and best known methods.
• Be a focal point for place and route, driving the work among place and route engineers.
• Resolve design and flow issues related to physical design and drive execution.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.