This role is part of the Silicon Technologies group, focusing on designing and manufacturing high-performance, power-efficient processors and system-on-chip (SoC). As a member of the CAD team, you will be responsible for architecting, developing, maintaining, and improving physical design verification (PDV) flows. You will collaborate with various teams, including custom digital, analog, mixed-signal design, and physical design. The position also involves developing rule decks and exploring automation solutions using machine learning and large language models.

• Minimum requirement of a BS degree with 0 years of experience.
• Knowledge in Silicon chip design flows.
• Understanding of DRC and LVS from previous work experience or coursework.
• Scripting experience in programming languages such as Python, Perl, or Tcl.
• Experience with automation and development.
• Knowledge of ML or LLM is a plus.

• Develop, improve, and maintain various aspects of physical verification flow and methodology.
• Coordinate the effort of validating flows and improving custom checks and data generation.
• Work with the design and PD teams to facilitate the chip design process.
• Code custom PDV rule decks such as Electrical rule checks and Programmable ERCs.
• Collaborate with tool vendors and foundries for PDK performance enhancements.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.