In this role at Apple, you will be responsible for the physical implementation of design partitions for a complex SOC. You will collaborate closely with architecture, CAD, timing, and logic design teams to ensure best-in-class designs. The position requires a strong understanding of chip architecture and back-end design flow. You will also be involved in resolving design issues and driving execution to meet project goals.

• Minimum BS degree with 0+ years of experience.
• Basic understanding of logic gates.
• Previous internship, co-op, project work, or relevant coursework in computer architecture, VLSI, design, logic design, or circuit design.
• Strong teamwork skills with the ability to collaborate with multiple functional teams.
• Experience with Verilog, VHDL, Python, Perl, TCL, and/or SPICE.

• Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle.
• Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals.
• Perform timing, physical and electrical verification, and drive the signoff closure for the partitions.
• Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.