JobsCAD Engineer - Timing for Gate-Level Flows & Methodologies
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CAD Engineer - Timing for Gate-Level Flows & Methodologies

Apple

Location

USA (Multiple Locations)

Type

Full-time

Posted

5/5/2026

Compensation

Not listed

Undergraduate with 5+ Years of Experience
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·FY 2025

Job description

This role is part of the STA CAD team within Apple's Silicon Technologies group, focusing on improving the performance of Apple Silicon. The team is responsible for developing and enhancing static timing analysis methodologies to ensure efficient timing closure for high-performance processors and system-on-chip designs. You will work closely with design teams and EDA vendors to address timing challenges and drive improvements in STA flows. This position requires a deep understanding of timing analysis and the ability to communicate effectively with various stakeholders.

Requirements

  • Minimum requirement of a BS degree and 10 years of relevant industry experience.
  • Expert power user of static timing analysis tools and flows.
  • Advanced programming skills with Python and Tcl or other high-level programming languages.
  • Proven track record of development and deployment of complex CAD flows and automation.
  • Familiarity with STA of large high-performance SoC designs in deep sub-micron technologies.
  • Deep understanding of noise, cross-talk, variation, margins, and timing models.
  • Knowledge of timing/SDC constraints with hands-on experience in creation and validation of constraints.
  • Excellent communication skills to assess and describe issues to management.

Responsibilities

  • Develop, maintain, and enhance existing gate-level STA flows for Apple silicon designs.
  • Work with design teams to understand and debug issues related to constraints, flow scripts, and timing closure.
  • Facilitate and drive STA methodology changes to improve overall STA flows as it relates to efficiency and productivity.
  • Develop and maintain scripts and methods for timing analysis and power reduction.
  • Develop and support methodologies, tools, and flows used in the verification of timing constraints.
  • Analyze timing paths to identify key issues, including post-silicon timing debug.
  • Work closely with EDA vendors to develop and incorporate new capabilities to solve technical problems.

Benefits

  • Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.

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