In this role at Apple, you will be responsible for the physical implementation of design partitions for a complex System on Chip (SoC) using advanced process technology. You will collaborate with design teams to debug constraints and facilitate logic changes to enhance timing. The position requires a strong focus on timing analysis and the creation of documentation and guidelines. Your contributions will help ensure the successful tapeout of groundbreaking Apple products.

• Minimum Bachelor's degree with 0+ years of experience
• Experience with Static Timing Analysis (STA)
• Familiarity with noise, crosstalk, and/or On-Chip Variation (OCV) effects
• Knowledge of timing aspects of large high-performance SoC designs in sub-micron technologies
• Good programming skills with Perl and TCL
• Familiarity with ECO techniques and implementation

• Work with design teams to understand and debug constraints and facilitate logic changes to improve timing
• Collaborate with the Physical Design team to highlight issues and best practices
• Help create timing Engineering Change Orders (ECOs) for project tapeout
• Create and maintain scripts and methodologies for analysis and runs
• Create documentation and assist with guidelines and specifications
• Conduct deep analysis of timing paths to identify key issues
• Implement timing infrastructure

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.