The ASIC RTL Design Engineer role at Google focuses on shaping the future of AI/ML hardware acceleration through the development of custom silicon solutions, particularly Tensor Processing Units (TPUs). The engineer will work within a dynamic team responsible for designing and building hardware that powers Google's services. This position involves driving innovation and contributing to complex digital designs, ensuring they meet performance and integration requirements. The role offers the opportunity to work on cutting-edge technology that impacts millions of users worldwide.

• PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• Experience in silicon engineering through internships, academic research, or publications.
• Proficiency in a scripting language such as Python or Perl.
• Experience in Verilog or SystemVerilog.

• Develop SystemVerilog RTL to implement logic for ASIC products.
• Create and review design microarchitecture specifications.
• Develop methodology and tooling for design automation.
• Work with Design Validation teams to create test plans to verify and debug design RTL.
• Collaborate with Physical Design teams to ensure design meets physical requirements and timing closure.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.