The SoC Silicon Top-Level Floorplan Engineer at Google will play a crucial role in shaping the future of AI/ML hardware acceleration. This position involves driving the development of cutting-edge TPU technology that supports Google's AI/ML applications. The engineer will work on creating the initial physical layout of chip top-level designs, collaborating with various teams to ensure optimal performance, power, and area goals. This role is central to the innovation behind products used by millions worldwide.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in physical design with a focus on floorplanning, integration, or top-level chip assembly.
• Experience in 3D Integrated Circuit design, including multi-die partitioning and TSV planning.
• Experience collaborating with cross-functional teams such as architecture, RTL design, synthesis, and verification.

• Own the planning, creation, and delivery of top-level floorplan deliverables for Silicon SOC projects.
• Resolve structural or physical issues related to the integration of ASICs and SoCs.
• Manage all cross-functional interactions related to top-level floorplanning of chip projects.
• Develop and improve floorplan implementation methodologies and support implementation flows.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.