The Power and Performance Architect for TPU at Google will shape the future of AI/ML hardware acceleration by driving cutting-edge TPU technology. This role involves defining and executing the power architecture roadmap for next-generation TPU SOCs. The architect will bridge high-level architectural concepts with silicon execution, ensuring effective implementation of power management features. The position requires collaboration with multidisciplinary teams to align silicon capabilities with system-level power constraints.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 15 years of experience in the design or definition of computer chips such as SOC, CPU, GPU, or hardware accelerators.
• Experience with performance analysis or performance modeling.
• Experience with power analysis, power modeling, or power delivery systems.

• Lead the definition of power architecture for the next generation of TPU SOCs, optimizing for performance-per-watt across machine learning workloads.
• Bridge the architecture-to-execution gap by partnering with SOC implementation, IP providers, and hardware and software validation teams.
• Drive the design and integration of power management features, including dynamic voltage and frequency scaling, power gating, and thermal mitigation strategies.
• Collaborate with the software community and data center teams to provide technology roadmaps that align silicon capabilities with system-level power constraints.
• Provide technical leadership and mentorship across multidisciplinary teams to anticipate future data center architectures and define SOC requirements.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.