The ASIC Power Management Architect role at Google focuses on developing custom silicon solutions that enhance the performance and efficiency of Google's products. The team aims to innovate and create hardware experiences that are both powerful and seamless. This position involves driving architectural analysis and collaborating with various teams to improve key performance indicators. The architect will leverage their expertise in ASIC power management to shape the future of technology at Google.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with ASIC power management architecture.
• Experience with hardware or software power control flows and methodology.
• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science is preferred.
• Experience with power components, power modeling, and power management techniques.

• Drive architectural analysis for mempath traffic patterns and collect silicon traffic patterns for key tensor CUJs.
• Oversee end-to-end correlation from pre-silicon micro benchmark power estimates to CUJ modeling estimates.
• Propose architectural features and requirements for mempath to improve overall Key Performance Indicators.
• Perform algorithm development, modeling, and analysis of various architecture approaches.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.