The Senior Signal and Power Integrity Engineer at Google will be part of a team focused on developing custom silicon solutions for Google's products. This role involves working on chip package design with signal and power integrity simulation at various levels. The engineer will collaborate with system architects, ASIC engineers, and other teams to ensure optimal performance and integration. The position emphasizes innovation in hardware experiences that enhance efficiency and reliability.

• Bachelor's degree in Mechanical Engineering, Material Engineering, Electrical Engineering, Technology, Science, or a related field.
• 4 years of experience in SI/PI design for chip/package or system PCB.
• Experience in industry SI/PI modeling tool chains such as HFSS, ADS, Sigrity, and Siwave.
• Excellent programming and data analysis skills with MATLAB, Python, C++, or similar.

• Drive SI/PI analysis and optimization for HPC based on 2.5D/3D technology.
• Lead the development of next-generation memory interfaces and evaluate high-speed interface IP.
• Manage post-silicon validation and qualification of high-speed interfaces for New Product Introduction.
• Partner with chip/system design teams and external vendors to define SI/PI design goals.
• Develop innovative methodologies to enhance simulation accuracy and productivity.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.