As a Timing Engineer at Apple, you will be part of the Wireless SoC organization, focusing on the development of energy-efficient wireless silicon. You will collaborate with SoC architects and IP developers to create SoCs that meet power, performance, and area goals. This role emphasizes improving design processes and tools while ensuring high-quality delivery through targeted checks. You will play a critical role in the ASIC creation effort, interfacing with various disciplines to launch leading-edge products.

• Bachelor's degree in a relevant field.
• 3+ years of relevant industry experience.
• Strong knowledge of the entire ASIC design process, from RTL through synthesis, static timing analysis, and place & route.
• Expertise in STA tools and flow.
• Proficient in scripting languages such as TCL, PERL, and Python.
• Familiarity with DFT approaches and constraints.

• Develop timing constraints (SDC) at partition and chip level.
• Execute logic synthesis from Verilog RTL to netlist.
• Utilize UPF for power and voltage islands.
• Address timing corners, operating modes, process variation, and signal integrity-related issues.
• Ensure closure of end-to-end logic equivalence with functional ECOs.
• Collaborate with multi-disciplinary groups to deliver designs on time and with high quality.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.