This role is for a design verification engineer at Apple, focusing on producing fully functional first silicon for IP designs. The engineer will work within a diverse team to develop verification methodologies and environments that ensure high-quality products. The position emphasizes the importance of pre-silicon verification, including test-plan development and debug processes. Candidates should be prepared to tackle complex challenges and contribute to the development of innovative technologies.

• BS degree in a technical subject area
• A minimum of 10 years of relevant industry experience
• Deep knowledge of OOP, SystemVerilog, and UVM
• Strong experience with verification methodologies and tools such as simulators and coverage collection
• Working experience using LLMs for efficiency and quality
• Excellent knowledge of one of the scripting languages such as Python, Perl, or TCL

• Establish DV methodology and develop test plans for verification.
• Develop verification environments including stimulus, checkers, and assertions.
• Execute verification plans and debug test failures.
• Track and report DV progress using various metrics.
• Develop detailed test and coverage plans based on micro-architecture.
• Ensure a scalable and portable verification environment.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.