As a Design Verification Engineer at Apple, you will play a critical role in verifying the functionality and performance of Apple's premier SOCs. You will collaborate closely with design, architecture, and micro-architecture teams to ensure the quality of the SOC or an IP or subsystem. This position requires a deep understanding of functional and performance goals to develop effective test plans and methodologies. You will be part of a dedicated team that drives innovation and excellence in chip design.

• Minimum of a BS degree with 0 years of relevant industry experience.
• Knowledge of computer architecture and digital design fundamentals.
• Knowledge of Verilog or SystemVerilog, digital simulation, and debug.
• Experience with Python, Perl, or a similar scripting language.
• Ability to work independently to deliver project goals.
• Experience with C/C++ and assembly is a plus.
• Excellent interpersonal skills and a desire to take on diverse challenges.

• Review design and architecture specifications.
• Develop test plans, tests, and coverage plans.
• Define next generation verification methodology and testbenches.
• Communicate and collaborate with design, architecture, and software teams.
• Understand use cases and corner conditions to drive test cases.
• Run and triage regressions, track bugs, and analyze coverage.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.