The Design Verification Engineer at Apple plays a crucial role in verifying the functionality and performance of Apple's premier SOCs. This position involves collaborating with various teams to ensure the quality of SOCs, IPs, or subsystems. The engineer will develop test plans and methodologies while actively communicating with design and architecture teams. This role offers the opportunity to focus on specific IPs or work across multiple subsystems.

• Minimum of a BS degree and 10 years of relevant industry experience.
• Skilled in digital verification processes including constrained random verification, functional coverage, and assertion methodology.
• Knowledge of SystemVerilog, digital simulation, and debugging.
• Good software programming skills with an understanding of data structures and algorithms.
• Experience with Python, Perl, or similar scripting languages.
• Knowledge of verification methodologies like UVM.
• Experience with C/C++ and assembly is a plus.

• Verify the functionality and performance of SOCs and subsystems.
• Review design and architecture specifications.
• Develop test plans, tests, and coverage plans.
• Collaborate with design, architecture, and software teams to understand use cases.
• Drive test cases based on functional and performance goals.
• Ensure the quality of the SOC or an IP or subsystem.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.