The Design Verification Engineer role at Apple involves verifying the functionality and performance of Apple's premier SOCs. This position is critical within the Hardware Technology team, where collaboration with various teams is essential. The engineer will ensure the quality of SOCs or subsystems by reviewing design specifications and working closely with design and micro-architecture teams. The role also emphasizes developing test plans and methodologies to achieve high-quality results.

• Minimum of a BS degree with 0 years of relevant industry experience.
• Knowledge of computer architecture and digital design fundamentals.
• Knowledge of Verilog or SystemVerilog, digital simulation, and debug.
• Experience with Python, Perl, or similar scripting languages.
• Experience with C/C++ and assembly is a plus.
• Excellent interpersonal skills and a desire to take on diverse challenges.

• Review design and architecture specifications to ensure quality.
• Develop test plans, tests, and coverage plans for SOCs.
• Define next-generation verification methodology and testbenches.
• Communicate and collaborate with design, architecture, and software teams.
• Run and triage regressions, track bugs, and analyze coverage.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.