JobsEmulation Verification Engineer
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Emulation Verification Engineer

Apple

Location

USA (Multiple Locations)

Type

Full-time

Posted

5/8/2026

Compensation

Not listed

Undergraduate with 2+ Years of Experience
Approval 98.9%·Filings 5,543·New hires 2,691·
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·FY 2025

Job description

The role involves joining Apple's design verification team to focus on the creation, deployment, and support of sophisticated emulation environments for chip design. You will collaborate with various teams including Architecture, Design, and Software to verify large System on Chips (SoCs) using emulation. The position requires a strong background in design verification and the ability to develop and apply monitors, checkers, and stimulus on the emulation platform. This is a dynamic role that plays a critical part in ensuring high-quality functional products are delivered to millions of customers.

Requirements

  • Minimum of a BS degree and 10 years of relevant industry experience.
  • Understanding of the tool flow from RTL to Emulation.
  • Good understanding of any Standard Emulator (Palladium, Veloce, Zebu) or FPGA (Xilinx, Altera) flow.
  • Proven design verification skills.
  • Experience in writing synthesizable SystemVerilog/Verilog code and SystemVerilog assertions.
  • Experience with SystemVerilog verification environments including C/C++ DPI and UVM.
  • Experience with writing and debugging test firmware.
  • Experience in any scripting languages such as Perl, Python, or TCL.
  • Excellent analytical and debugging skills.
  • Experience in UVM Acceleration is a plus.

Responsibilities

  • Collaborate closely with Architecture, Design, DV, Silicon Validation, Power, and Software teams to bring up large SoCs on the emulation platform.
  • Develop and apply synthesizable monitors, checkers, and stimulus on the emulation platform.
  • Prepare and complete the test plan and perform reviews with multi-functional teams.
  • Perform low power testing on the emulation platform.
  • Develop code for design and verification that aids with emulation activities using Verilog, System Verilog, or UVM.
  • Develop random stimulus infrastructure by reusing existing UVM simulation constraints.

Benefits

  • Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.

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