This role at Apple focuses on ensuring bug-free first silicon for SoC/IP by developing detailed test and coverage plans based on micro-architecture. The position involves creating a scalable and portable verification environment and executing verification plans for various features. The team works on pre-silicon verification of complex IO protocols and develops post-silicon sequences for validation. Candidates will engage in a collaborative environment that fosters innovation and diversity.

• Bachelor's degree or foreign equivalent in Electronic Engineering, Electrical Engineering, or a related field.
• 5 years of progressive, post-baccalaureate experience in the job offered or related occupation.
• 3 years of experience performing Constraint Random Verification using Universal Verification Methodology (UVM).
• 3 years of experience developing Verification IPs using System Verilog and Universal Verification Methodology (UVM).
• 3 years of experience implementing System Verilog and System Verilog Assertions coding.
• 3 years of experience scripting using TCL/Perl or Python.
• 3 years of experience in microcontroller/CPU based SOC/IP verification.
• 3 years of experience implementing and verifying pre-silicon design to prototyping platforms like Emulation.
• 3 years of experience debugging pre-silicon failures with industry standard tools like Verdi or Indago.
• 3 years of experience in DFT verification with JTAG/1500 standards in a pre-silicon environment.

• Ensure bug-free first silicon for part of the SoC/IP.
• Develop detailed test and coverage plans based on the micro-architecture.
• Create a scalable and portable verification environment.
• Develop verification environment components such as stimulus, checkers, assertions, trackers, and coverage.
• Execute verification plans, including design bring-up and DV environment bring-up.
• Track and report DV progress using various metrics, including bugs and coverage.
• Work on pre-silicon ser-des PHY verification of complex IO protocols like PCIe and Usb4.
• Develop verification environment for manufacturing screening DFT patterns.
• Create post-silicon sequences from the verification environment for reuse in silicon validation.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.