As an ASIC STA Engineer at Apple, you will be integral to the chip design process, focusing on timing analysis and closure for advanced SoCs. You will work with a world-class modem team to ensure that Apple products maintain their industry-leading connectivity performance. This role requires collaboration with various teams to resolve complex timing issues and improve existing methodologies. Your contributions will directly impact the performance of Apple’s in-house 5G modem platforms and other products.

• Bachelor's degree in Electrical Engineering (BSEE) or Computer Science (BSCS) is required.
• Knowledge in ASIC timing constraints generation and timing closure.
• Good knowledge in STA tools such as Primetime and methodologies for timing closure.
• Proficient in scripting languages including Tcl and Perl/Python.
• MS degree is preferred.

• Own timing sign-off to ensure timing requirements are met across all corners, modes, and conditions.
• Generate block and full chip timing constraints.
• Collaborate with multi-functional teams to resolve sophisticated timing issues.
• Manage timing/SDC constraints generation and ensure effective timing closure.
• Implement improvements to existing methodologies and flows.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.