This role is for a design verification engineer at Apple, focusing on producing fully functional first silicon for IP designs. The engineer will work on pre-silicon verification, developing methodologies, test plans, and verification environments. The position requires a mindset to identify and resolve design issues while ensuring a scalable and portable environment. The engineer will also leverage LLM technologies to enhance efficiency and quality in the verification process.

• BS degree in a technical subject area
• Minimum 10 years of relevant industry experience
• Deep knowledge of OOP, SystemVerilog, and UVM
• Strong experience with verification methodologies and tools
• Working experience using LLMs for efficiency and quality
• Excellent knowledge of one of the scripting languages such as Python, Perl, or TCL

• Establish DV methodology and develop test plans for verification.
• Develop verification environments including stimulus, checkers, and assertions.
• Ensure bug-free first silicon for parts of the SoC/IP.
• Execute verification plans and debug test failures.
• Track and report DV progress using various metrics.
• Develop scalable and portable test-benches for the IP.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.