This role is for a design verification engineer at Apple, focusing on producing fully functional first silicon for IP designs. The engineer will work on pre-silicon verification, developing methodologies and test plans to ensure bug-free silicon. The position involves creating a scalable and portable verification environment and utilizing advanced technologies for improved efficiency. The engineer will also track and report progress using various metrics.

• BS degree in a technical subject area
• A minimum of 10 years of relevant industry experience
• Deep knowledge of OOP, SystemVerilog, and UVM
• Strong experience with verification methodologies and tools
• Working experience using LLMs for efficiency and quality
• Excellent knowledge of one of the scripting languages such as Python, Perl, or TCL

• Establish DV methodology and develop test plans.
• Develop verification environment including stimulus, checkers, and assertions.
• Execute verification plans and debug test failures.
• Develop block, IP, and SoC level test-benches.
• Track and report DV progress using metrics such as bugs and coverage.
• Make use of LLM and related technologies to achieve efficient execution.

• Employees at Apple are often offered comprehensive benefits that support physical and mental well-being—flexible medical plans, confidential counseling, onsite wellness centers at major campuses, and resources for fitness and daily life. Families typically receive fertility support, paid parental leave with gradual return, caregiving leave, and dependent-care guidance, while financial perks commonly include stock grants (with purchase discounts), 401(k) matching, and income-protection coverage. Employees also see robust time off, Apple University learning and tuition reimbursement, donation matching and paid volunteer hours, and deep product and partner discounts.