NVIDIA is seeking a Senior Power Integrity Engineer to join the LPU Packaging team, focusing on defining and optimizing power delivery design practices across various levels of product development. The role involves collaborating with design teams and driving system-level power integrity design while utilizing advanced simulation tools. This position is crucial for ensuring the performance and reliability of NVIDIA's cutting-edge products, particularly in the realms of AI and high-performance computing. The ideal candidate will have extensive experience in power integrity for high-current, low-voltage applications.

• MS or PhD in Electrical Engineering or a related field, or equivalent experience
• 12+ years of relevant work experience in Power Integrity
• A strong background in power integrity for high-current, low-voltage rails within large GPUs, ASICs, or CPUs
• Proven ownership of the chip-package-board PDN design and sign-off process
• Hands-on experience with FCBGA, 25D/3D integration, HBM, or similar high-power, high-pin-count packages
• Proficiency with frequency-domain PDN impedance analysis and time-domain transient/droop simulation tools
• A deep understanding of board-level PDN design, including stack-up definition, plane partitioning, and VRM placement on high-layer-count accelerator boards
• Experience in executing lab measurements using VNAs, oscilloscopes, and PDN analyzers

• Define best-in-class power delivery design and optimization practices from die/package through board, tray, and rack levels for the full product development cycle
• Own the PI specification and methodology for assigned products, defining PDN targets including impedance, droop, noise, and transient response for GPU, HBM, and high-speed SerDes
• Architect package-level PDNs by collaborating with design teams on bump/ball maps, via structures, and decoupling strategies for FCBGA and 25D/3D integrations
• Drive system-level PI design, including board-level PDN planning, decap placement, and VRM interfaces while co-optimizing with SI, thermal, and mechanical teams
• Perform PI extraction and simulation for advanced packages and develop integrated chip–package–board co-simulation flows using industry-standard tools
• Generate and deploy reusable PI models, such as SPICE, S-parameter, and IBIS-AMI, for use by internal and external partners
• Define and execute comprehensive lab validation plans to correlate measured impedance, noise, and droop against simulation data and specifications
• Debug complex system-level issues including rail noise, jitter-induced errors, resets, and margin loss during hardware testing and validation

• Employees at NVIDIA are often offered comprehensive, day-one benefits—including medical, dental, and vision coverage with HSA support, life and disability insurance, an Employee Assistance Program, and a 401(k) with auto-enrollment. Many roles also have generous time off and holidays, donation matching (up to $10,000), and a wide menu of extras like FSAs, commuter benefits, legal and identity-theft protection, pet insurance, and wellness discounts. Optional programs can include student-loan and home-purchase support, plus family care resources and expert medical services.