Intel is seeking a talented and motivated Physical Design Floorplanning Engineer to join their team. This role focuses on top-down SoC floorplan activities, collaborating with architects and other stakeholders to optimize IP placement and manage multi-power domain planning. The engineer will drive execution and supervise progress of smaller blocks or sub-systems to achieve optimal physical dimensions and area. This position offers the opportunity to work on cutting-edge technology advancements that empower people's digital lives.

• Bachelor in Electrical/Electronics/Computer Engineering with 3+ years of relevant experience or Master's degree with 2+ years of relevant experience.
• 2+ years of experience using industry-standard EDA tools for floorplanning and APR.
• 1+ years of experience with multi-power domain designs.
• 1+ years of experience with Synopsys Fusion Compiler.
• 3+ years of experience with TCL, Python or Perl programming.
• 2+ years of experience with Calibre or ICV verification.

• Conduct top-down SoC floorplan activities including IP placement, partitioning, and multi-power domain planning.
• Estimate die-area and define optimal physical dimensions for SoCs considering product costs and technology selection.
• Drive execution and supervise progress of smaller blocks or sub-systems to optimize area and convergence schedule.
• Plan short and long-term work schedules while understanding dependencies between different design domains.
• Collaborate with stakeholders to deliver physical block level floorplans for APR and manage metal allocation for signal and power.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.