As a Physical Design Timing Engineer at Intel, you will be integral in enhancing the performance and efficiency of DDRPHY IP design. Your role will involve timing analysis, optimization, and clock network design, contributing to high-performance, low-power solutions. You will collaborate with various teams to influence methodologies and ensure design robustness. This position offers a unique opportunity to impact Intel's innovative technologies significantly.

• Bachelor's degree with 6+ years of experience, or Master's degree with 4+ years of experience, or PhD with 2+ years of experience in Electrical Engineering, Computer Engineering, or a related field.
• 2+ years of experience in static timing analysis tools and methodologies.
• Expertise in clock design, timing budgeting, and constraint adaptation.
• Hands-on experience with TCL scripting for flow development and optimization.
• Strong technical knowledge of physical design fundamentals, including extraction, noise glitch analysis, and signal integrity.
• Familiarity with FEM/PV scaling methods and library characterization.

• Perform chip/block-level timing analysis and optimization for IP, identifying and resolving violations to ensure functionality and performance targets are met.
• Generate and verify timing constraints, conducting timing rollups for efficient physical design processes.
• Design and optimize power and performance-efficient clock networks, ensuring adherence to product requirements.
• Develop and refine methodologies for high-quality timing models to streamline physical design workflows.
• Define process, voltage, and temperature (PVT) conditions for timing analysis based on operating conditions and product binning plans.
• Collaborate with architecture, clock design, and logic design teams to develop integration workflows and validate clock network guidelines.
• Work closely with backend design teams for clock balance, timing corrections, power delivery, and partitioning strategies.
• Conduct noise glitch and signal integrity analysis, ensuring design robustness under diverse conditions.
• Contribute to tools, flows, and methodology (TFM) development to support efficient implementation and optimization processes.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.