The DFT ATPG engineer is responsible for developing logic designs and providing DFT timing closure support, including test content generation for manufacturing. This role involves collaborating on architecture and microarchitecture features of various DFx content. The engineer will optimize logic to meet design goals and ensure high-quality integration of DFT blocks into functional IP and SoC. Additionally, the position requires collaboration with post-silicon and manufacturing teams to verify features on silicon and drive high test coverage.

• BS EE/CE or related STEM field with 3+ years of relevant DFT experience or MS EE/CE or related STEM field with 1+ years of relevant DFT experience.
• 1+ years of experience in tools like Siemens Tessent, Spyglass, Fusion compiler, and/or VCS.
• 1+ years of experience with scan insertion, low coverage debug, GLS debug, and/or post silicon debug.

• Develop logic design and RTL coding for DFT.
• Provide DFT timing closure support and generate test content for manufacturing.
• Collaborate in defining architecture and microarchitecture features.
• Optimize logic to meet power, performance, area, timing, and test coverage goals.
• Review verification plans and drive verification of DFT designs.
• Integrate DFT blocks into functional IP and SoC.
• Collaborate with post-silicon and manufacturing teams to verify features on silicon.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.