The Pre-Silicon IP Design Verification Engineer role at Intel's Devices Development Group focuses on validating IP or features at the IP level for next-generation SOCs. The team is dedicated to reimagining computing technology and ensuring high-quality designs through rigorous testing and validation. This position involves engaging with various stakeholders to streamline IP development and SOC integration. The engineer will also develop debugging tools and methodologies to enhance the validation process.

• Must have either a BS + 2 years' experience or MS + 1 years' experience in Computer Science, Computer Engineering or Electrical Engineering.
• Minimum 2 years experience with reading and interpreting technical specs and Register Transfer Level (RTL) code.
• Minimum 2 years experience working on IP or SoC development, verification, or integration using Verilog/SystemVerilog and OVM/UVM.
• Minimum 2 years experience with writing validation plans and software to implement those validation plans.
• Minimum 2 years experience with an object oriented programming language.
• Minimum 2 years experience with Verilog or other HDL.
• Minimum 1 years experience with UNIX or Linux.

• Validate an IP or feature at the IP level.
• Create plans and tests for validating portions of a complex microarchitecture using written specs, RTL code and other tests as a guide.
• Learn architecture and microarchitecture by debugging failures to the root cause.
• Develop and utilize various debug and validation tools and/or methodologies to implement validation plans.
• Participate in the debug of failures on silicon and develop new testing strategies to detect these failures on RTL models.
• Engage with IP providers and customers to define, develop and deliver necessary infrastructure and address issues found during execution.
• Develop tools and methods to streamline IP development and SOC integration.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.