As a Silicon Packaging Design Engineer at Intel, you will be integral to the development of advanced substrate designs that enhance the company's technological leadership. This role involves managing the entire development process of substrate designs, collaborating with silicon and hardware teams to optimize performance and cost efficiency. You will contribute to innovative solutions that address global computing challenges. This position offers a unique opportunity to work on cutting-edge technologies in a dynamic team environment.

• Bachelor's degree in Electrical Engineering, Mechanical Engineering, or Material Sciences with 0-1+ years of relevant experience.
• Experience with package design tools such as Siemens Xpedition, Cadence Allegro Package Design, AutoCAD, or SolidWorks.
• Experience with physical layout aspects of substrate design, including custom layouts and schematic layout conversions.
• US Citizenship is required.
• This position is not eligible for Intel sponsorship.

• Drive the physical layout and routing of package designs to meet performance requirements.
• Conduct substrate fit and routing studies to establish design and cost tradeoffs.
• Define and implement substrate design rules and conduct reviews to maintain quality standards.
• Analyze data, resolve Design Rule Checks (DRCs), and optimize designs for manufacturability.
• Collaborate with cross-functional teams to optimize pinout and silicon-package-board interactions.
• Complete documentation and collateral into the product lifecycle management system.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.