The role is part of the Advanced Design Foundation IP group within the Design Technology Platform at Intel. The team focuses on designing foundational collateral for Intel's CPU and SoC products, ensuring they meet density and performance scaling goals. The position involves collaboration with various teams to optimize design and technology, delivering silicon-proven solutions. The successful candidate will drive library PDK releases and develop guidelines for passive components.

• Bachelor's degree in electrical engineering or related STEM field with 4+ years in analog/RF circuit design or device physics fundamentals, or a Master's degree with 3+ years, or a Ph.D. with 6+ months of experience.
• 3+ years' experience with SPICE level circuit design/simulation and Cadence Virtuoso or equivalent custom design environment.
• 3+ years' experience in data analysis/scripting, such as Python or Matlab.

• Drive on-time library PDK release with the highest quality, coordinating with design owners and multiple stakeholders.
• Ensure timely development and test coverage for passive component templates.
• Define copy exact foundational IP in collaboration with analog and RF designers.
• Work with process device and reliability stakeholders as part of DTCO to optimize design and process modeling.
• Design library collateral schematics and layouts for passive components and characterize them through all PV RV and electrical parameter extraction flows.
• Develop and maintain template design guidelines and best practices for MFC, TFR, and other passive components.
• Collaborate with modeling teams to ensure accurate electrical models for designed templates.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.