Intel is seeking physical design engineers to join its neuromorphic silicon team, focusing on innovation at the intersection of semiconductor technology and novel computing paradigms. The team is dedicated to transforming research breakthroughs into real-world products that will advance physical AI systems. Candidates will play a hands-on role in ensuring designs meet performance, area, power, and scan coverage targets. An openness to learning new technologies and methodologies is essential for success in this role.

• Bachelor's degree with 4+ years of hands-on physical design experience, or a Master's degree with 3+ years, or a PhD.
• 3+ years of experience in synthesis, place and route, and timing/layout closure.
• 3+ years of experience with scripting languages such as Perl, TCL, or Python.

• Understand design dataflow and chip-level floor-planning constraints to set up partition floorplans with macro/pin placements and keep-outs.
• Work with RTL designers to define timing constraints and run synthesis and place-and-route trials.
• Fix timing, EM/IR, and DRC violations as needed.
• Run back-annotated VCS+SDF simulations and iterate on meeting power/performance targets.
• Write custom scripts and define tool flows to manipulate synthesis and physical design tools for low power/high performance custom designs.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.