As a Silicon Packaging Design Engineer at Intel, you will be integral to the development of advanced substrate designs that drive innovation in high-performance applications. This role involves collaborating with silicon and hardware teams to ensure optimal performance and manufacturability of package designs. You will manage the end-to-end development process, from concept to tape-out, while focusing on cost efficiency and quality standards. This position offers the opportunity to directly impact Intel's success in delivering cutting-edge technology.

• Bachelor's degree with 1+ years of experience or a master's degree with 6 months of experience in Electrical Engineering, Mechanical Engineering, or Material Sciences.
• 6+ months of experience with microelectronic package or PCB physical layout design and manufacturing processes.
• Familiarity with package design tools like Siemens Xpedition, Cadence Allegro Package Design, AutoCAD, or SolidWorks.
• Understanding of physical layout aspects of substrate design, including custom layouts and schematic layout conversion.

• Drive the physical layout and routing of package designs to meet performance requirements.
• Perform substrate fit and routing studies to establish design, performance, and cost tradeoffs.
• Define and implement substrate design rules while conducting internal and external reviews.
• Analyze data, resolve Design Rule Checks (DRCs), and optimize package designs for manufacturability.
• Collaborate with cross-functional teams to optimize pinout and silicon-package-board interactions.
• Complete documentation and collateral into the product lifecycle management system.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.