JobsPrincipal Engineer, Design Technology Co-optimization
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Principal Engineer, Design Technology Co-optimization

Intel

Location

USA (Multiple Locations)

Type

Full-time

Posted

5/10/2026

Compensation

$220,920 - $311,890 per year

Undergraduate with 5+ Years of Experience
Approval 96.6%·Filings 2,117·New hires 632·
💎 Strong Sponsor
·FY 2025

Job description

The role of logic library vertical lead involves optimizing standard cell libraries on Intel's advanced process nodes to meet the needs of both internal and external foundry customers. The position is part of the Advanced Design & Foundational IP team, which focuses on design-technology co-optimization and foundational IP development. The lead will work closely with physical design engineers and EDA partners to enhance cell performance, power, and area. This position requires strong technical expertise in semiconductor technology and a collaborative mindset.

Requirements

  • Ph.D. or master's degree in electrical engineering or computer science
  • 10+ years of industry experience
  • Strong technical understanding of advanced semiconductor technology
  • Strong technical understanding of foundation IP design and design-technology co-optimization
  • Experience in standard cell library design with a good understanding of MOSFET electrical characteristics
  • Experience with library cell characterization methodology and tools and Spice circuit simulations
  • Experience in semiconductor foundry ecosystem from foundry, EDA/IP, or foundry customer perspective
  • Excellent oral and written communication skills
  • Collaborative mindset and great team player
  • Good track record of technical leadership and delivery

Responsibilities

  • Drive optimization of standard cell libraries on Intel's leading edge process nodes
  • Interface with key Intel foundry customers to understand technology and library gaps
  • Collaborate with Intel foundry technology development teams and EDA partners for co-optimization
  • Optimize library circuits in close collaboration with physical design engineers
  • Provide optimally tuned layout to improve cell performance, power, and area
  • Collaborate with EDA partners to optimize cell content in the standard cell library

Benefits

  • Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.

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