The Memory Debug Engineer role within the Client Customer Engineering team at Intel focuses on driving the enablement, validation, and debugging of memory subsystems for next-generation Intel IA-based platforms. This position requires strategic oversight of memory IO interfaces to ensure they meet electrical performance and stability standards. The engineer will work closely with cross-functional teams and external customers to resolve architectural bottlenecks and complex issues. The role emphasizes leadership in managing task forces to address critical bugs and improve product quality.

• The candidate must have a BS/MS/PhD in Electrical Engineering or Computer Engineering with 4+ years of industry experience.
• 3+ years of experience with DDR4/DDR5, LPDDR4/5 protocols and physical layer functionality.
• 3+ years of experience with debug tools such as high-speed oscilloscopes, logic analyzers, margining tools, profilers, and protocol exercisers.

• Define and execute the overarching validation and debug strategy for memory IO interfaces.
• Lead the reproduction and root-cause analysis of high-priority customer-submitted failure sightings.
• Ensure all customer memory IO interfaces meet industry-standard electrical signal integrity compliance.
• Define Memory Reference Code requirements for validation and margin optimization.
• Act as the primary liaison between Intel Silicon Engineering, BIOS/Firmware teams, and the customer.
• Manage and drive task force environments to resolve critical bugs.
• Communicate complex electrical eye-diagram issues into executive-ready insights and recommendations.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.