The Silicon Design Verification Engineer for Quantum AI at Google will be a key member of the quantum electronics team, focusing on ASIC design verification for future quantum computers. This role involves collaborating with digital, physical design, and RF/analog engineers to implement complex ASICs for control and readout. The engineer will drive the verification lifecycle, ensuring thorough testing and coverage of designs. This position offers the opportunity to contribute to groundbreaking technology that powers Google's consumer products.

• Bachelor's degree in Electrical Engineering or a related technical field, or equivalent practical experience.
• 4 years of experience in silicon design verification using SystemVerilog/UVM.
• Experience with SOC verification including CPUs, bus interfaces, or peripherals.
• Experience in scripting languages such as Python or Perl for automation and analysis.

• Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers.
• Develop and maintain constrained-random verification environments using System Verilog and Universal Verification Methodology (UVM).
• Create and execute verification plans and test cases, identifying and debugging verification failures.
• Close coverage measures to identify verification holes and show progress towards tape-out.
• Integrate any verification IP for externally developed IP into the overall verification flow.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.