JobsSOC Physical Design Static Timing Analysis Engineer
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SOC Physical Design Static Timing Analysis Engineer

Intel

Location

Phoenix, AZ, Santa Clara, CA

Type

Full-time

Posted

5/14/2026

Compensation

$164,470 - $311,890 per year

Undergraduate with 5+ Years of Experience
Master's with 5+ Years of Experience
PhD with 5+ Years of Experience
Approval 96.6%·Filings 2,117·New hires 632·
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·FY 2025

Job description

As a Physical Design Timing Engineer at Intel, you will be instrumental in enhancing the performance and power efficiency of System-on-Chip (SoC) designs. Your role involves collaborating with various teams to optimize high-performance solutions and develop methodologies that improve operational excellence. This position offers the opportunity to work on complex designs that have a significant global impact. You will contribute to groundbreaking advancements in technology that drive computing innovation.

Requirements

  • Bachelor's degree with 8+ years, master's degree with 6+ years, or PhD with 4+ years in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • 7+ years of technical proficiency in SOC level static timing analysis, clock network design, and timing closure methodologies.
  • 3+ years of experience in timing constraint adaptation, physical design knowledge, and optimization techniques.
  • Proficiency with industry-standard tools for timing analysis, extraction, and physical design.
  • Familiarity with TCL scripting and timing budgeting processes.

Responsibilities

  • Perform SOC level timing analysis and optimization to ensure designs meet functional and performance requirements.
  • Generate and verify timing constraints while addressing timing violations at the chip or block level for SoCs.
  • Conduct timing rollups and develop optimized clock networks for functionality, performance, and power efficiency.
  • Define methodologies to produce high-quality timing models and enable efficient physical design execution.
  • Establish appropriate process, voltage, and temperature conditions for timing analysis, aligning with product plans and binning strategies.
  • Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning.
  • Collaborate with architecture, clocking design, DFT, and logic design teams to develop flows for chip integration and validate clock network performance guidelines.
  • Contribute to the development of tools, flows, and methodologies that enhance SoC physical design and timing processes.

Benefits

  • Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.

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