AMD's Datacenter Performance Group is looking for motivated engineers to enhance the Power Constrained Performance of AI/ML/HPC GPUs. The role focuses on various aspects of performance at power, including pre-silicon power modeling, workload analysis, and setting performance targets. Candidates should be passionate about performance and power efficiency and possess strong analytical skills. Collaboration with engineers across different locations is essential for success in this position.

• Background in Computer Architecture, Power and Performance
• Experience in SoC Level Power/Performance projections, modeling, and optimization
• Experience in power modeling for digital and analog IPs
• Familiarity with digital logic physical design and power management techniques
• Verilog RTL coding experience or understanding, especially in low power design techniques
• Experience in post-silicon power/performance debug and model correlation
• Knowledge of DL/ML/LLM workloads is a bonus
• Fluency in Excel-based data analysis and charting, with scripting experience in Ruby and Python

• Conduct pre-silicon power modeling for HW-IP, SoC, and Multi-GPU nodes/clusters
• Support pre-silicon PPA target setting for hardware IPs, firmware, and software
• Collaborate with various engineering functions to support PPA attainment
• Perform post-silicon calibration of models and conduct power/performance debugging
• Analyze key workloads for power behaviors and identify optimization opportunities
• Script and code to automate routine tasks and build new tools for wider usage

• AMD provides a competitive 'Total Rewards' package that focuses on financial growth, health, and work-life balance.