The SoC Design Engineer for the Tensor Processing Unit at Google will focus on shaping the future of AI and ML hardware acceleration. This role involves working on SoC-level RTL design for data center accelerators, contributing to the development of custom silicon solutions. The engineer will collaborate with various ASIC development teams and will be responsible for defining methodologies that enhance the design environment. This position offers the opportunity to tackle challenging technical problems in a dynamic and collaborative setting.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 2 years of experience architecting RTL solutions using software-based construction.
• Experience with industry-standard EDA tools for simulation, synthesis, and power analysis.

• Define and document the microarchitecture for digital designs within the TPU.
• Develop high-quality, performant, and power-efficient Register Transfer Level (RTL) code, primarily in SystemVerilog.
• Partner with the Verification team to develop test plans, debug RTL, and ensure functional correctness.
• Work closely with the Physical Design team to meet timing, area, power, and manufacturability requirements.
• Contribute to the development and enhancement of design tools, flows, and methodologies.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.