This role is focused on developing logic design and RTL coding for SoC designs within Intel's AI SoC organization. The ideal candidate will work in a fast-paced environment, integrating IP blocks and subsystems into full chip designs while ensuring design integrity. The position involves collaboration with verification teams and applying various strategies to optimize logic for power, performance, area, and timing goals. The engineer will also mentor junior engineers and contribute to best practices in design methodology.

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science
• 7+ years of experience in RTL design and implementation for ASIC/SoC development

• Lead evaluation of architectural trade-offs considering features, performance targets, power constraints, and system limitations.
• Define and document micro-architecture for complex SoC IP blocks and implement RTL in Verilog/SystemVerilog.
• Collaborate closely with verification teams to ensure comprehensive coverage and robust validation of all design aspects.
• Develop and maintain timing constraints for IP blocks and provide guidance to physical design teams.
• Drive silicon bring-up and post-silicon validation, including debug and performance analysis.
• Mentor junior engineers and contribute to best practices for design methodology and quality.

• Intel offers a comprehensive benefits package including competitive pay, stock programs, healthcare coverage, retirement plans, paid time off, parental leave, and programs supporting employee wellbeing and professional development.