The Design Verification Engineer role at Google focuses on developing custom silicon solutions for the company's direct-to-consumer products. The team aims to innovate and enhance hardware experiences that deliver exceptional performance and efficiency. This position requires collaboration with design engineers to ensure the functionality of digital design blocks. The engineer will utilize their expertise in verification methodologies to contribute to the development of cutting-edge technologies.

• Bachelor's degree in Electrical Engineering, Computer Science, a related field, or equivalent practical experience.
• 4 years of experience verifying digital logic at RTL using SystemVerilog.
• Experience verifying digital IP and subsystems.
• Master's degree in Electrical Engineering, Computer Science, a related field, or equivalent practical experience is preferred.
• Experience creating and utilizing UVM-based verification environments is preferred.
• Familiarity with ASIC standard interfaces and memory system architecture is preferred.

• Plan the verification of complex digital design blocks by analyzing specifications and collaborating with design engineers.
• Develop and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM).
• Design and implement comprehensive coverage measures to target functional stimulus and corner-case scenarios.
• Debug test failures in collaboration with design engineers to ensure functionally correct digital blocks.
• Analyze coverage data to identify verification gaps and track progress toward tape-out milestones.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.