As an ASIC Design Verification Engineer at Google, you will play a crucial role in shaping the future of AI/ML hardware acceleration by verifying complex digital designs, specifically focusing on TPU architecture. You will collaborate with design and verification engineers to enhance verification environments and ensure the functionality of design blocks. This position is part of a team that drives innovation in custom silicon solutions, impacting Google's AI/ML applications. Your expertise will contribute to the full lifecycle of verification, from planning to execution.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience with design verification.
• Experience with SystemVerilog/Verilog.
• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science is preferred.
• 6 years of experience with silicon design verification is preferred.
• Experience with scripting languages such as Python or Perl is preferred.

• Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers.
• Create and enhance constrained-random verification environments using SystemVerilog and UVM.
• Identify and write coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to ensure functionally correct design blocks.
• Close coverage measures to identify verification holes and demonstrate progress towards tape-out.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.