The Static Timing Analysis Engineer will be part of a team focused on developing custom silicon solutions for Google's products. This role involves driving the timing closure and chip integration processes to ensure high-performance and efficient designs. The engineer will leverage their expertise in static timing analysis to contribute to the innovation of hardware experiences. This position is critical in shaping the next generation of technology that enhances user experiences worldwide.

• Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
• 4 years of technical experience in silicon timing closure and chip integration.
• Experience in one or more static timing tools such as PrimeTime or Tempus.
• Experience with Static Timing Analysis (STA) signoff constraint authoring for full-chip level.

• Deliver system-on-chip (SoC) Static Timing Analysis.
• Define SoC timing signoff process corners, derates, uncertainties and their tradeoffs.
• Drive clock tree Jitter and implementation for SoCs to achieve best energy, performance and area.
• Execute full chip timing constraint validation and timing signoff checklist criteria.

• Employees at Google are often offered benefits like comprehensive health insurance, 401(k) matching, and flexible work arrangements, among other benefits.